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kinda finished wiring

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This commit is contained in:
nek0 2020-02-28 06:04:10 +01:00
parent 8695a00c1a
commit 1ec58912cb
4 changed files with 1467 additions and 397 deletions
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40
fauxie_module/fauxie_module-cache.lib
View file

@ -18,6 +18,30 @@ X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Transistor_BJT_PZT2222A
#
DEF Transistor_BJT_PZT2222A Q 0 0 Y N 1 F N
F0 "Q" 200 75 50 H V L CNN
F1 "Transistor_BJT_PZT2222A" 200 0 50 H V L CNN
F2 "Package_TO_SOT_SMD:SOT-223-3_TabPin2" 200 -75 50 H I L CIN
F3 "" 0 0 50 H I L CNN
$FPLIST
SOT?223*
$ENDFPLIST
DRAW
C 50 0 111 0 1 10 N
P 2 0 1 0 0 0 25 0 N
P 2 0 1 0 100 -100 25 -25 N
P 2 0 1 0 100 100 25 25 N
P 3 0 1 20 25 75 25 -75 25 -75 N
P 3 0 1 0 90 -90 70 -70 70 -70 N
P 5 0 1 0 45 -65 65 -45 85 -85 45 -65 45 -65 F
X B 1 -200 0 200 R 50 50 1 1 I
X C 2 100 200 100 D 50 50 1 1 P
X E 3 100 -200 100 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# fauxie_module-rescue_+3.3V-power
#
DEF fauxie_module-rescue_+3.3V-power #PWR 0 0 Y Y 1 F P
@ -319,6 +343,22 @@ X C 3 200 -100 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# power_+3V3
#
DEF power_+3V3 #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+3V3" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS +3.3V
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +3V3 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_+5V
#
DEF power_+5V #PWR 0 0 Y Y 1 F P

1474
fauxie_module/fauxie_module.kicad_pcb
View file

File diff suppressed because it is too large Load diff

257
fauxie_module/fauxie_module.pro
View file

@ -1,29 +1,10 @@
update=Mi 26 Feb 2020 23:27:18 CET
update=Fr 28 Feb 2020 05:57:58 CET
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
@ -41,3 +22,239 @@ NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.25
TrackWidth2=0.25
ViaDiameter1=0.8
ViaDrill1=0.4
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.051
SolderMaskMinWidth=0.25
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.25
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[pcbnew/Netclasses/1]
Name=Power
Clearance=0.2
TrackWidth=0.8
ViaDiameter=0.8
ViaDrill=0.6
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25

93
fauxie_module/fauxie_module.sch
View file

@ -516,10 +516,8 @@ F 3 "" H 7050 1300 50 0001 C CNN
$EndComp
Text Label 3600 2400 2 50 ~ 0
Dat_in
Text Label 6650 1800 0 50 ~ 0
Text Label 8500 3150 0 50 ~ 0
Dat_in
Wire Wire Line
6650 1800 6550 1800
Wire Wire Line
3600 2400 3700 2400
$Comp
@ -556,4 +554,93 @@ NoConn ~ 6550 2100
NoConn ~ 6550 2300
NoConn ~ 6550 2500
NoConn ~ 6550 2900
$Comp
L Transistor_BJT:PZT2222A Q1
U 1 1 5E58DDBB
P 7300 3050
F 0 "Q1" V 7535 3050 50 0000 C CNN
F 1 "PZT2222A" V 7626 3050 50 0000 C CNN
F 2 "Package_TO_SOT_SMD:SOT-223-3_TabPin2" H 7500 2975 50 0001 L CIN
F 3 "http://www.fairchildsemi.com/ds/PN/PN2222A.pdf" H 7300 3050 50 0001 L CNN
1 7300 3050
0 1 1 0
$EndComp
$Comp
L Device:R R3
U 1 1 5E59BC22
P 7650 2850
F 0 "R3" V 7443 2850 50 0000 C CNN
F 1 "2.2k" V 7534 2850 50 0000 C CNN
F 2 "Resistor_SMD:R_0603_1608Metric" V 7580 2850 50 0001 C CNN
F 3 "~" H 7650 2850 50 0001 C CNN
1 7650 2850
0 1 1 0
$EndComp
$Comp
L Device:R R4
U 1 1 5E59C7C3
P 7950 2900
F 0 "R4" H 8020 2946 50 0000 L CNN
F 1 "6.8k" H 8020 2855 50 0000 L CNN
F 2 "Resistor_SMD:R_0603_1608Metric" V 7880 2900 50 0001 C CNN
F 3 "~" H 7950 2900 50 0001 C CNN
1 7950 2900
1 0 0 -1
$EndComp
$Comp
L Device:R R5
U 1 1 5E59D6AE
P 8250 3150
F 0 "R5" V 8043 3150 50 0000 C CNN
F 1 "470" V 8134 3150 50 0000 C CNN
F 2 "Resistor_SMD:R_0603_1608Metric" V 8180 3150 50 0001 C CNN
F 3 "~" H 8250 3150 50 0001 C CNN
1 8250 3150
0 1 1 0
$EndComp
$Comp
L power:+3V3 #PWR061
U 1 1 5E5AC9F0
P 7800 2750
F 0 "#PWR061" H 7800 2600 50 0001 C CNN
F 1 "+3V3" H 7815 2923 50 0000 C CNN
F 2 "" H 7800 2750 50 0001 C CNN
F 3 "" H 7800 2750 50 0001 C CNN
1 7800 2750
1 0 0 -1
$EndComp
$Comp
L power:+5V #PWR060
U 1 1 5E5AD866
P 7950 2650
F 0 "#PWR060" H 7950 2500 50 0001 C CNN
F 1 "+5V" H 7965 2823 50 0000 C CNN
F 2 "" H 7950 2650 50 0001 C CNN
F 3 "" H 7950 2650 50 0001 C CNN
1 7950 2650
1 0 0 -1
$EndComp
Wire Wire Line
7800 2750 7800 2850
Wire Wire Line
7500 2850 7300 2850
Wire Wire Line
8500 3150 8400 3150
Wire Wire Line
8100 3150 7950 3150
Wire Wire Line
7950 2650 7950 2750
Wire Wire Line
7950 3050 7950 3150
Connection ~ 7950 3150
Wire Wire Line
7950 3150 7500 3150
Text Label 7000 3150 2 50 ~ 0
Dat
Wire Wire Line
7000 3150 7100 3150
Text Label 6650 1800 0 50 ~ 0
Dat
Wire Wire Line
6650 1800 6550 1800
$EndSCHEMATC