58 lines
No EOL
2.3 KiB
Text
58 lines
No EOL
2.3 KiB
Text
EESchema-LIBRARY Version 2.3
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#encoding utf-8
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#(c) SnapEDA 2016 (snapeda.com)
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#This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License (CC BY-SA) with Design Exception 1.0
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#
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# STM8S103K3T6C
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#
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DEF STM8S103K3T6C U 0 40 Y Y 1 L N
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F0 "U" -901 1622 50 H V L BNN
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F1 "STM8S103K3T6C" -870 -1801 50 H V L BNN
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F2 "QFP80P900X900X160-32N" 0 0 50 H I L BNN
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F3 "LQFP-32 STMicroelectronics" 0 0 50 H I L BNN
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F4 "STM8S103K3T6C" 0 0 50 H I L BNN
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F5 "None" 0 0 50 H I L BNN
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F6 "STMicroelectronics" 0 0 50 H I L BNN
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F7 "Mainstream Access line 8-bit MCU with 8 Kbytes Flash, 16 MHz CPU, integrated EEPROM" 0 0 50 H I L BNN
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F8 "Unavailable" 0 0 50 H I L BNN
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DRAW
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P 2 0 0 10 -900 1600 900 1600 N
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P 2 0 0 10 900 1600 900 -1700 N
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P 2 0 0 10 900 -1700 -900 -1700 N
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P 2 0 0 10 -900 -1700 -900 1600 N
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X NRST 1 -1100 1500 200 R 40 40 0 0 I
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X OSCIN/PA1 2 -1100 1400 200 R 40 40 0 0 B
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X OSCOUT/PA2 3 -1100 1300 200 R 40 40 0 0 B
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X VSS 4 1100 -1600 200 L 40 40 0 0 W
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X VCAP 5 1100 1200 200 L 40 40 0 0 P
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X VDD 6 1100 1500 200 L 40 40 0 0 W
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X PA3/TIM2_CH3[SPI_NSS] 7 -1100 1200 200 R 40 40 0 0 B
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X PF4 8 -1100 -1600 200 R 40 40 0 0 B
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X PB7 9 -1100 300 200 R 40 40 0 0 B
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X PB6 10 -1100 400 200 R 40 40 0 0 B
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X PB5/I2C_SDA 11 -1100 500 200 R 40 40 0 0 B
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X PB4/I2C_SCL 12 -1100 600 200 R 40 40 0 0 B
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X PB2/AIN2/TIM1_CH3N 14 -1100 800 200 R 40 40 0 0 B
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X PB3/AIN3/TIM1_ETR 13 -1100 700 200 R 40 40 0 0 B
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X PB1/AIN1/TIM1_CH2N 15 -1100 900 200 R 40 40 0 0 B
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X PB0/AIN0/TIM1_CH1N 16 -1100 1000 200 R 40 40 0 0 B
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X PE5/SPI_NSS 17 -1100 -1500 200 R 40 40 0 0 B
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X PC1/TIM1_CH1/UART1_CK 18 -1100 100 200 R 40 40 0 0 B
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X PC3/TIM1_CH3 20 -1100 -100 200 R 40 40 0 0 B
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X PC2/TIM1_CH2 19 -1100 0 200 R 40 40 0 0 B
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X PC4/TIM1_CH4/CLK_CCO 21 -1100 -200 200 R 40 40 0 0 B
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X PC5/SPI_SCK 22 -1100 -300 200 R 40 40 0 0 B
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X PC7/SPI_MISO 24 -1100 -500 200 R 40 40 0 0 B
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X PC6/SPI_MOSI 23 -1100 -400 200 R 40 40 0 0 B
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X PD0/TIM1_BKIN[CLK_CCO] 25 -1100 -700 200 R 40 40 0 0 B
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X PD1/SWIM 26 -1100 -800 200 R 40 40 0 0 B
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X PD2[TIM2_CH3] 27 -1100 -900 200 R 40 40 0 0 B
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X PD3/TIM2_CH2/ADC_ETR 28 -1100 -1000 200 R 40 40 0 0 B
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X PD4/BEEP/TIM2_CH1 29 -1100 -1100 200 R 40 40 0 0 B
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X PD5/UART1_TX 30 -1100 -1200 200 R 40 40 0 0 B
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X PD7/TLI[TIM1_CH4] 32 -1100 -1400 200 R 40 40 0 0 B
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X PD6/UART1_RX 31 -1100 -1300 200 R 40 40 0 0 B
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ENDDRAW
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ENDDEF
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#
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# End Library |